The present application claims priority to Japanese Application(s) No(s). P2000-309506 filed Oct. 10, 2000, and P2001-147024 filed May 16, 2001, which application(s) is/are incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, particularly to a semiconductor formed by mounting a semiconductor chip on an interposer substrate and the manufacturing method therefor.
2. Description of the Related Art
In the semiconductor chip having a plurality of elements built therein and circuit patterns formed thereon, the pitch among the electrodes which are formed on one surface of the semiconductor chip is very small. As a result, if such a semiconductor chip is directly mounted on a motherboard, there is a risk that the electrodes peel off, or that the semiconductor chip is damaged, since there is a large difference in the thermal expansion coefficient between the semiconductor chip and the motherboard. Accordingly, a semiconductor device is used wherein a semiconductor chip is mounted on one surface of an interposer substrate which is a size larger than the semiconductor chip, wherein electrodes having a larger pitch than that of the electrodes on the semiconductor chip are formed on the other surface of the interposer substrate, and wherein the semiconductor device is mounted on the motherboard making use of these electrodes of the interposer substrate.
FIG. 11 shows a conventional semiconductor device 1 as described above. The semiconductor 1 is mounted on an interposer substrate 2. Solder bumps 3 are affixed on electrodes 4 and on the bottom surface of the semiconductor chip. The solder bumps 3 are bonded, by soldering, to the electrodes 4 which are formed on the surface of the interposer substrate 2 and each of which is constituted of a conductor pattern. As a solder for connecting the solder bumps 3 to the conductor patterns 4, a solder having a melting point lower than that of the solder of the solder bumps 3 is used.
In this manner, the semiconductor chip 1 mounted on the interposer substrate 2 becomes mechanically strong, and the distance between adjacent electrodes on the interposer substrate 2 can be made larger than the distance between adjacent electrodes on the semiconductor chip 1, so that mounting works with the interposer substrate 2 and semiconductor chip 1 are facilitated.
The reliability of bonding the semiconductor chip shown in FIG. 11 to the motherboard by soldering involves a problem. That is, as the motherboard, a substrate formed of an organic material which is inexpensive and relatively flexible is generally used, but such a substrate requires giving consideration to a sufficient relaxation of thermal stress.
In the flip-chip mounting method, wherein the electrode surface of the semiconductor chip 1 is used as a bonding surface with the interposer substrate 2, a ceramic material which is expensive and relatively hard, an aramid material which has an elastic modulus close to that of the semiconductor chip 1, or the like is employed. Also, when a film-shaped flexible substrate is used, a resin is interposed between the semiconductor chip and the flexible substrate, thereby both the flexible substrate and the semiconductor chip are fixedly adhered with reliability. Therefore, even if the semiconductor chip itself presents no problem, a problem of stress concentration occurs at the solder bonding portion between the electrodes on the interposer substrate and the connecting lands of the motherboard. It is difficult, therefore, to adopt the LGA (Land Grid Array) method, which is a method of forming connecting lands with solder without using solder bumps, and which is difficult to absorb stress.
When using a built-up substrate as a conventional interposer substrate 2, a construction wherein any surface of the interposer substrate is constituted of a built-up layer is used. Herein, since the top surface of the interposer substrate 2 constitutes the mounting surface of the semiconductor chip 1, the built-up layer of this mounting surface requires flatness and a low thermal expansion coefficient. In contrast, the built-up layer on the bottom surface side of the interposer substrate 2 constituting a bonding surface with the motherboard, requires the stress relaxation function required when connected to the motherboard, so that this built-up layer must be formed of a material having flexibility, or, low elastic modulus.
Hence, in the interposer substrate 2, the built-up layer at the portion to be bonded to semiconductor chip 1 above the interposer substrate 2 must be made of a relatively hard material, while the built-up layer on the bottom surface side of the interposer substrate to be bonded to the motherboard must be made of a soft material. This means that mutually different type of materials are employed for the interposer substrate. This raises problems in that the manufacturing cost of interposer substrate 2 increases and the manufacturing process thereof becomes complicated.
The present invention has been achieved to solve the above-described problems, and the object thereof is to provide a semiconductor device which allows the reliability of the connection of the interposer substrate to the semiconductor chip and the reliability of the connection of the chip-size package to the motherboard to be compatible with each other, and to provide the manufacturing method therefor.
In order to achieve the above-described object, the present invention provides a semiconductor device comprising a silicon semiconductor chip which has a plurality of circuit elements built therein and circuit patterns formed thereon using the diffusion technique or the like, and which has a plurality of electrodes formed on the outer surface thereof; an interposer substrate on which the semiconductor chip is mounted; a core substrate constituting the base of the interposer substrate; built-up layers built on only one surface of the core substrate; an anisotropic conductive layer which is formed on the other surface of the core substrate, and via which the semiconductor chip is mounted on the core substrate. In this semiconductor device, electrodes on the core substrate and those on the semiconductor chip are electrically connected via the anisotropic conductive layer.
Herein, the built-up layers formed on the core substrate may have an elastic modulus of 5000 MPa (SI unit) or below. Also, the elastic modulus of the built-up layers may be smaller than or equal to a half of that of the core substrate. The built-up layers may have curved wiring patterns formed on the surface thereof so as to relax stress. Also, the core substrate may be formed of a material having a thermal expansion coefficient relatively close to that of the semiconductor chip, and the core may have a thickness of 0.5 mm or below.
On the surface of the core substrate on which the built-up layers are formed, the patterns subjected to the pressing force in the bonding of the anisotropic conductive layer may be formed at the positions corresponding to the electrodes of the semiconductor chip. The arrangement may be such that the interposer substrate is constructed by forming a plurality of built-up layers on the core substrate, that electrodes are formed so as to pass through the outermost built-up layer, and that these electrodes constitute electrodes connected to the motherboard.
The method for manufacturing the semiconductor device in accordance with the present invention comprises preparing an interposer substrate by forming built-up layers on one surface of a core substrate; mounting the semiconductor chip, via an anisotropic conductive layer, on the other surface opposite to the one surface on which the built-up layers of the core substrate have been formed; and electrically connecting the electrodes on the semiconductor chip and those on the other surface of the core substrate via the anisotropic conductive layer.
The method for manufacturing the semiconductor device in accordance with the present invention may be such that holes are formed in a built-up layer; the surface of the built-up layer including the holes are plated with a conductive metal, the plated layer is etched; and thereby wiring patterns and vias (conductive portions) are simultaneously formed on the built-up layer. By repeating these processes, a plurality of built-up layers is successively formed on one surface of the core substrate.
Here, preferred embodiments of the present invention will be listed below.
(1) A semiconductor device using one-side built-up layer substrate wherein no built-up layer is formed on the semiconductor mounting surface of the core substrate constituting the base of the interposer substrate, and wherein the arrangement is such that the semiconductor chip is stably connected onto the wiring pattern formed on the semiconductor mounting surface of the core substrate via an anisotropic conductive layer.
(2) A semiconductor device having a structure in which the built-up layers formed on the surface of the core substrate opposite to the semiconductor mounting surface has a flexible physical property such as to preferably have an elastic modulus of 5000 MPa or below, and more preferably 2500 MPa or below, and which allows the warp of the core substrate and the stress on the motherboard to be relaxed.
(3) A semiconductor device which is arranged to have a plurality of built-up layers, and to make the shape of the pattern interposed between the built-up layers a curved wiring pattern, and to relax thermal stress by virtue of this curved shape.
(4) A semiconductor device which is arranged so that the core substrate thereof constituting the base of the interposer substrate is a thin substrate formed of a material having a low thermal expansion coefficient, such as an glass-fiber epoxy resin, and that the interposer substrate preferably has a thickness of 0.5 mm or below, and more preferably 0.2 mm or below, and that the stress due to the difference in the thermal expansion between the semiconductor chip and the core substrate is reduced.
(5) A semiconductor device wherein a semiconductor chip is mounted on the interposer substrate thereof, and wherein reinforced patterns subject to a pressing force when adding the pressing force to the anisotropic conductive layer for connecting the electrodes of this semiconductor chip and those of the interposer substrate, are formed on the rear surface of the core substrate.
(6) A semiconductor device in which no lead-out of the wiring is formed on the lower portion of the interposer substrate, and below the reinforced pattern subject to a pressing force of the anisotropic conductive layer connecting the electrode of the semiconductor chip and that of the core substrate, and which thereby allows through-holes to be formed under the above-described reinforced pattern, in the motherboard.
(7) A semiconductor device which does not require forming a protective resist for protecting wiring on the surface of the core substrate, on the surface of the core substrate carrying the semiconductor chip, the surface having no built-up layer formed.
Here, the thermal expansion coefficient of silicon is about 2 to 3 ppm/C. xc2x0. As the core substrate 12, a glass-fiber epoxy resin substrate having a thermal expansion coefficient of about 5 to 13 ppm/C. xc2x0, which is relatively close to the thermal expansion coefficient of silicon. Meanwhile, a first built-up layer 13 and a second built-up layer 14 are each constituted of a resin layer such as an epoxy resin layer or a bismuth imide resin layer having a thermal expansion coefficient of about 80 to 100 ppm/C. xc2x0.
With regard to the elastic modulus, as the core substrate 12 in accordance with this embodiment, constituted of a glass fiber epoxy resin, one which has an elastic modulus of 10,000 to 30,000 MPa was used. As the first and second built layers 12 and 13, one which has an elastic modulus of 3,500 MPa or below, that is, one which is more flexible than the core substrate.
The above and other objects, features, and advantages of the present invention will be clear from the following detailed description of the preferred embodiments of the invention in conjunction with the accompanying drawings.